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Reduced instruction set computing (RISC)

Reduced instruction set computing, or RISC (pronounced ‘risk’), is a CPU design strategy based on the insight that a simplifiedinstruction set provides higher performance when combined with a microprocessor architecture capable of executing those instructions using fewer microprocessor cycles per instruction.[1] A computer based on this strategy is a reduced instruction set computer, also called RISC. The opposing architecture is called complex instruction set computing (CISC).

Various suggestions have been made regarding a precise definition of RISC, but the general concept is that of a system that uses a small, highly optimized set of instructions, rather than a more versatile set of instructions often found in other types of architectures. Another common trait is that RISC systems use the load/store architecture,[2] where memory is normally accessed only through specific instructions, rather than accessed as part of other instructions like add.

Although a number of systems from the 1960s and 70s have been identified as being forerunners of RISC, the modern version of the design dates to the 1980s. In particular, two projects at Stanford University and University of California, Berkeley are most associated with the popularization of this concept. Stanford’s design would go on to be commercialized as the successful MIPS architecture, while Berkeley’s RISCgave its name to the entire concept, commercialized as the SPARC. Another success from this era were IBM‘s efforts that eventually led to thePower Architecture. As these projects matured, a wide variety of similar designs flourished in the late 1980s and especially the early 1990s, representing a major force in the Unix workstation market as well as embedded processors in laser printersrouters and similar products.

RISC families include DEC AlphaAMD Am29000ARCARMAtmel AVRBlackfinIntel i860 and i960MIPSMotorola 88000PA-RISCPower (including PowerPC), RISC-VSuperH, and SPARC. In the 21st century, the use of ARM architecture processors in smart phones and tablet computers such as the iPad and Android devices provided a wide user base for RISC-based systems. RISC processors are also used in supercomputers such as the K computer, the fastest on the TOP500 list in 2011, second at the 2012 list, and fourth at the 2013 list,[3][4] and Sequoia, the fastest in 2012 and third in the 2013 list.